Hi,
- Its "Analog Devices" AD9689.
- I can't tell much at the moment, i can only say that the sync signal is deasserting in a very short periods of time. if you can tell me what signals to look for i can do a more-intensive tests. as for screen shots, im not sure i will be able to supply them, but if you can address me to which signals to look for i could have more data about this.
- i don't currently have a simulation of the IP itself. im assuming it should work since it worked with previous quartus version. were there any changes to the ip that could actually account to a functional difference? i checked the release notes, its didn't seemed to have anyting about such a functional diffrence...
- its not gonna be easy to get the qsys file out to send, maybe ill be able to get it, how ever, i can say that iuts set to be just a reciever, with subcalss 1, Enabled Soft PCS and that the PLL/CDR Clock is 220. if you have any question about a specific parameter, let me know.
about 5,6 - thanks you very much, i wasn't aware for these sections in the guide. ill check these right away and let you know.
Thanks.
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