JESD204B device clk

Hi!

That does work! I must confess I tried to use fPLL but my mistake was to use fPLL as a buffer for routing device clk from input FPGA pin to feed JESD core pll.

Now I set one fPLL as JESD core PLL according to your advice and it works!

The one thing I have not realized at the moment - why did you advice me to use HSMC_B more than HSMC_A? HSMC_A has the same number of receiver pairs as HSMC_B and I compiled the project for HSMC_A and device clk pin H17, H16.

Thanks in advance for your help!