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Altera_Forum
Honored Contributor
10 years agoJESD204B device clk
Hi! My task is to develop and debug JESD204B based measurement system. I have a DEV-ADC34J22 board connected to Cyclone V GT development kit through HSMC connector. The adc board has HSMC_C...
Altera_Forum
Honored Contributor
10 years agoFor more info, you can consult the Cyclone V handbook vol. 2 here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v3.pdf
The table on P63/P64 (Table 2-1) shows the clock sources for the transceivers. Note that for JESD we need the CDR blocks, so you need a clock source that says 'Yes' in that column of which only the three I identified above are available. If you scroll down a bit to the bottom of P66, it explains using the FPLL as a clock source.