JESD204B DEV_SYNC_N, Rx Link Up is LOW and dev_aligned is LOW

1. I have Arrira 10 SoC (p/n = 10AS066N2F40E2SG) on my new board.
2. I have 8 lanes JESD204B Rx connected to ADC12DJ3200.
3. I got signal tap for debug

So far,

1) - I got rx_is_lockedtodata[7:0] are HIGH with x"BCBCBC..." received on jesd204_rx_pcs_data (renamed to serdes_data_in) with jesd204_rx_pcs_data_valid is HIGH.

2) However the dev_sync_n stays in LOW so that the ADC won't send data to FPGA (jesd204).

3) attached is a screenshot on some of buses.

I would like to get your insights and suggestions. Thanks.