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User1580871742356367
Occasional Contributor
Occasional ContributorJESD204B DEV_SYNC_N, Rx Link Up is LOW and dev_aligned is LOW
I have Arrira 10 SoC (p/n = 10AS066N2F40E2SG) on my new board. I have 8 lanes JESD204B Rx connected to ADC12DJ3200. I got signal tap for debug So far, 1) - I got rx_is_lockedtodata[7:0] are HI...
Nathan_R_Intel
Contributor
ContributorHie,
Your signaltap is missing some critical signals such as sync_n; hence its difficult to make a concludion on what is going on.
Please add signal following Figure 33 of the user guide and refer to the description of the timing diagram to understand whats going wrong in your system.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf
Please check that and let me know if you have further questions.
Regards,
Nathan
