Forum Discussion
New ContributorJESD204B debug
Regular ContributorHi,
As I understand it, you are observing some problem with the JESD204B RX working with an ADC. Only one of the two boards is exhibiting this problem. The other board is working fine. I am assuming that both boards are the same and using the exact same FPGA design.
Based on the current observation, it seems to be related to the signal integrity problem which lead to data received corruption. To further narrow down this, you can try to do the following:
1. Use oscilloscope to probe as closest to the FPGA RX balls, check the eye diagram to see if can spot any anomaly.
2. Repeat the same for the good board and compare the eye diagram with the faulty to see if can spot any anomaly.
3. Check all the clocks on the faulty board to see if there is any anomaly.
4. You can use signaltap to check PHY status signals to further narrow down the problem. You may refer to table "PHY Status Signals for All Supported Devices Except Intel Stratix 10 E-tile
Devices" in the JESD204B IP user guide for the list of signals to monitor.
Please let me know if there is any concern. Thank you.
New ContributorThank you for the suggestions.
1. 2. Unfortunately I do not have the equipment to probe those high frequency signals.
3. I have not been able to check the ADC clock, but the other clocks looks good.
4. I did add those signals you suggested to signal tap and they all look good.
Next I made the signal tap file as described under Creating a Signal Tap Debug File to Match Your Design Hierarchy. I am currently in the process of trying to find any difference between the working board and the failing board.
