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David32's avatar
David32
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3 years ago

JESD204B deassembler

I am using Arria 10 to receive data from multiple ADCs (the ADC09QJ800 from TI). Each ADC device will be using JESD config as: 4 lanes 4 converters 8 bits per sample The deassembler code ge...
David32's avatar
David32
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Skbeh,

I really need a bit more help.

My design (with N = is not supported by the QSYS example designs.

In addition, the Transport Layer file generated by other QSYS example designs is not valid for N <12.

The IP core specific for my design outputs a bus of 128 bits.

All I want to know is the mapping of my samples into those 128 bits.

Please try and find an answer to this reasonable question.

Thank you,

David