Jesd204B compile failed

Question

Dear Support/Expert, 
This is a tricky question; I am using Intel A10 GX develop board to implement a data acquisition system, one side is TI AFE58JD48, 16 ADC chip. I set the parameters to 
1. both base and phy, 
2. Receiver.
3 subclass: 1.
4. 6144 MHz.
5 Enabled softPCS
6. 153.6MHz.
7. LMF = 4, 16, 8.  N = 16, S = 1.

Fitter will fail, I don't understand I config it to receiver only, why failed on Duplex_channel_cluster.  I attached the file that mentioned in the error message. but I don't understand how to solve this problem. 
Hope some JESD204B and transceiver expert can give me some help.
Best Regards,
David 
-----------------------
Error(14996): The Fitter failed to find a legal placement for all periphery components Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(14996): The Fitter failed to find a legal placement for all periphery components Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error: ERROR: An error occurred during automatic periphery placementError: Quartus Prime Fitter was unsuccessful. 29 errors, 12 warnings Error: Peak virtual memory: 3168 megabytes Error: Processing ended: Tue Jun 21 09:19:41 2022 Error: Elapsed time: 01:09:05 Error: System process ID: 5700 Error(293001): Quartus Prime Flow was unsuccessful. 31 errors, 6427 warnings Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(14986): After placing as many components as possible, the following errors remain: Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(175001): The Fitter cannot place 1 HSSI_DUPLEX_CHANNEL_CLUSTER, which is within JESD204B Intel FPGA IP xcvr_jesd_rx_jesd204_0_altera_jesd204_1920_refiuwi. Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below: Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error(177002): If the HSSI_DUPLEX_CHANNEL_CLUSTER is placed in the following regions, source auto-promoted clock driver cannot be routed Error: Peak virtual memory: 3168 megabytes Error: Processing ended: Tue Jun 21 09:19:41 2022 Error: Elapsed time: 01:09:05 Error: System process ID: 5700 
-----------------------

skbeh · Answer

Hi DavidThe twentynm_pma.zip that you attached only contains 1 file (twentynm_pma.sv), unable to compile.Please attach the Quartus project archive (.qar) so that I can compile to duplicate the error.In between, 'JESD204B Intel FPGA IP Core – Support Center' at below link include some Arria 10 JESD204B reference designs, worth to take a look and you might download these reference designs and modify according to your need. Thus, could avoid the compilation error due to wrong pin assignments.https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/jesd204b-support.html

dsun01 · Answer

Hi Skbeh,

Thank you very much for help. 
The whole design used 4 4-lane cores; I made a mistake will I assign the pins. now I can compile without problem.
in the meantime, I do have a very critical application question which I opened a new thread here.

Fundamental question about Jesd204B, Lanes VS ADCs - Intel Communities

if you have time, please give me some suggestions. 
Appreciate your help.
David

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Jesd204B compile failed

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