Contributor
ContributorHi David
The twentynm_pma.zip that you attached only contains 1 file (twentynm_pma.sv), unable to compile.
Please attach the Quartus project archive (.qar) so that I can compile to duplicate the error.
In between, 'JESD204B Intel FPGA IP Core – Support Center' at below link include some Arria 10 JESD204B reference designs, worth to take a look and you might download these reference designs and modify according to your need. Thus, could avoid the compilation error due to wrong pin assignments.
ContributorHi Skbeh,
Thank you very much for help.
The whole design used 4 4-lane cores; I made a mistake will I assign the pins. now I can compile without problem.
in the meantime, I do have a very critical application question which I opened a new thread here.
Fundamental question about Jesd204B, Lanes VS ADCs - Intel Communities
if you have time, please give me some suggestions.
Appreciate your help.
David
