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Altera_Forum
Honored Contributor
12 years agoJESD IP core: Same link clock shared between all transciever lanes
Hi All, Is it possible to use a common external reference clock for L lanes transceivers in JESD 204 IP core??or do we need separate external reference clock for each sets of lane?? Thanks...
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- Hi Gowtham, Great! Have you tested any of the JESD204B IP yet? I have not. I first wanted to start with some simple transceiver based designs, and then see if I can interface to the JESD204B links directly, and create my own (free) IP. Cheers, Dave --- Quote End --- Hi Dave, Sorry for the late reply. Regarding JESD204B IP i have also not yet tested any. I am actually working on dynamic reconfiguration of the transport layer IP provided by Altera. Thanks, Gowtham