New Contributor
Regular ContributorThe 10G protocol support in Multirate PHY IP is actually 10GBASE-R as show in attached pic.
New ContributorThe Multirate PHY requires a license whereas the L-Tile Native PHY does not. Therefore, I would like to know how to connect the Native PHY.
I read through the L-tile PHY user guide section 2.4.3 explaining the latency pulses. It shows that a latency calculation IP block is required to determine the total latency. How would this be used in a 1588 design? The MAC has a tx_path_delay and rx_path_delay inputs that usually come from the PHY. Would path delay inputs now need to be generated from the pulses? How is this accomplished?
Regular ContributorHi,
Unfortunately I won't be able to advise on the 1588 solution build with NativePHY IP as it's not part of solution package offered by Intel FPGA.
As you are aware, the 1588 feature support is available in Multirate-PHY IP.
So, it's a fair trade here. Either user pay for the solution or develop the solution by themselves.
Thanks.
Regards,
dlim
New ContributorOK.
Can you tell me if the example design implements the full PTP protocol stack? In other words, does it implement the Best Master Clock Algorithm, PTP state machine, etc? I am wondering if I can use the bulk of the example design in a project without much CPU interaction.
I can see in the simulation that it is sending some PTP SYNC and DELAY REQUEST packets but I don't see the TOD clocks being updated.
Thanks.
