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Altera_Forum
Honored Contributor
Honored ContributorIs it save to use the PIO in QSYS
Hello, I have several PIOs in my QSYS design to communicate with some of my own designed IPs. My IPs mostly use other clock signals than the PCIe-Clock and are therefore not synchronized to t...
Altera_ForumHonored Contributor
Honored ContributorI believe that one pulse or signal is input of the Pulsecounter module and based on this signal or pulse you are incrementing the counter.I think it will either generate latch or combination loop. Both can cause significant stability and reliability problems in design.I am sure that Quartus Design Assistant will report violation for your Pulsecounter design. So my suggestion is to try some other alternative.
