Is it possible to create an SRAM with Byte Enable and implement it on MLABs(Memory LABs) resources ?

I used the Verilog code below: module Memory( input we, clk, input [5:0] waddr, raddr, // address width = 6 input [3:0] be, // 4 bytes per word input [31:0] wdata, // byte width = 8, 4 bytes pe...