Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is DDR2 bursting?

Hi, Thanks for your answers. I could do the user controlled refresh on DDR2. But, now struck with another problem. We know that DDR memories work in a burst fashion. To describe in detail...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Small clrearification,

I checked in signal tap II logic analyzer that "read_data_valid" signal stays high once per 34 clock cycles for a read operation.

1) The module "tt_sahred_ddr2" sets the burst_count to 8.

but

2) local_size[6 downto 0] = 1. local_burstbegin is as expected.

(Note: I increased the "Maximum Local Interface Burst" to 64 now and hence local_size is 7 bits wide now.) Kindly, check the settings in the attached ZIP file and help me.

Thanks and best regards,

Hardik Shah