Altera_Forum
Honored Contributor
Honored ContributorIP core optimization
Hi everyone, How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?
Forum Discussion
Altera_ForumHonored Contributor
Honored ContributorHi I wrote http://nibz.googlecode.com using Quartus II, in the current incarnation nibz12.vhd the "ALTERA" generic is not used anywhere. The LUT usage is mainly controlled by the VHDL sythesizer setting of area, balanced or speed. The area option even provides more speed sometimes, but enable register retiming etc to get the exta nano second. Avoid long chains of carry propergation. Nibz although a 34 state state machi9ne, renders as a 5 state state machine in one hot technology. Why, I don't know.
So 4-LUT or arithmetic and/xor double 3-LUT (I think) *2 in each logic element with one general register/latch. Memory: use registered read for generality. cheers jacko
