Altera_Forum
Honored Contributor
Honored ContributorIP core optimization
Hi everyone, How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I am re-designing a existing fast Ethernet MAC IP... which needs to be fit in to Altera's small FPGA which should be optimized in both speed and area. I would like to reduce its size to round about less than 1000 LEs and 4-6 Kb internal memory usage. --- Quote End --- In the Quartus handbook, see Volume 2, Section III, "Area, Timing and Power Optimization". Within Quartus, run "Resource Optimization Advisor" and "Timing Optimization Advisor" at "Tools --> Advisors". Note that some optimizations that help area hurt speed and vice versa.
