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Altera_Forum
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17 years ago

IP core optimization

Hi everyone, How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?
Altera_Forum's avatar
Altera_Forum
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17 years ago

Thanks Harald! I am re-designing a existing fast Ethernet MAC IP (with limited feature to incorporate into an embedded system) which needs to be fit in to Altera's small FPGA which should be optimized in both speed and area. I would like to reduce its size to round about less than 1000 LEs and 4-6 Kb internal memory usage.

Thanks Frank! Can you please tell me which parameters need to be taken care of when optimizing IP cores for a specific vendor FPGA, for a time being lets take only Altera's FPGAs.