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Altera_Forum
Honored Contributor
Honored ContributorIP core optimization
Hi everyone, How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?
Altera_ForumHonored Contributor
Honored ContributorSorry, Ketan, but it's still not clear what you want to do. Optimizing something for FPGA implementation could mean to describe the logic in a way that the synthesis tools is able to implement it according to your needs that you still haven't said. Do you want highest speed? Then try to pipeline the logic so that only one LUT is needed between two registers stages. Or do you want smallest area? Or lowest power? You question is not specific enough by now.
