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Hi Bob,
Have you tried using the PCIe compiler GUI, and reading the PCIe Megacore Users Guide? The guide has screen shots and explains what the settings are. It sounds like all you want to do is to start the GUI, and edit the existing design to change the BAR sizes. If so, why? BAR sizes are usual set small, since you only ever use them to write to control registers. If you want to access anything like memory, then you should be using a DMA controller (its a lot faster for data transfer).
If you look at the PDF in the thread linked to above, it explains the settings in the PCIe GUI. It should be similar for your board.
Cheers,
Dave
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Dave, I still struggle with this .. the screen shot attached indicates that the Arria V isn't supported by the PCIe compiler ... I tried going through the compiler and megacore info. I am using the Avalon-MM Arria V Hard IP for PCI experess and it works but doesn't let me change the BAR sizes. ... So I have been modifying the
synthesize verilog manually where the core is instantiated. This is a problem when I come to run Modelsim since whatever Modelsim is compiling for its simulation
models doesn't seem to pick up my manual changes.
I have tried to change the attribute of the .tcl file which says if the file function can is "editable" but that doesn't seem to do anything.
Any ideas on this ... or can you say which simulation file I would edit to keep the synthesize file edits in synch with the Modelsim simulation ?
Thanks, Bob
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