IP AltsyncRam -- Read/Write operations issue

Hi,

I don't see why you get worried about first set of undefined data. Designs normally wash off initial values and look for some start flags e.g. start of a packet ...etc.

However if your design depends on that initial read then I can add one more bit to each location to flag '1' indicating that data was written and true.

You will need to initialise mem to zero first using a mif file.

Though this is overkill. You can also use simpler toggle logic if there is a pattern between write/read.