IP AltsyncRam -- Read/Write operations issue

Thanks all, I guess I have to think about modifying my pipeline so that no RAM location is read before something has been written to it first.

Or, as kaz said, discard 'x' values I get for every location that I read for the first time.

My RAM has 1024 addresses, 14-bit data, so I have to build a "map" of the locations read at least once and the ones never read.

Any suggestions to achieve that in logic would be much appreciated.

Thanks again to all, I am new to HDL design using RAM blocks, so I am learning here...