Forum Discussion
Altera_Forum
Honored Contributor
17 years agoIP AltsyncRam -- Read/Write operations issue
Hi all, I have another issue using the RAM IP core generated with the MegaFunction wizard. Here's the entity of my RAM and its instanciation:
GENERIC(
ADDRESS_WIDTH : IN INTEGER ;
PIXE...
Altera_Forum
Honored Contributor
17 years agoIt's RAM. If you don't write anything to an address, then the contents of that address are undefined. That is how RAM has always worked. Modelsim is essentially telling you "Hey nothing has been written to this location!". In which case you'd most certainly better not be using the data.
As far as the dummy read/write cycle thing. That's not the best way to phrase it. There is a one clock latency minimum for reads. Writes are performed on the clock cycle where the command is presented. Jake