IP AltsyncRam -- Read/Write operations issue

Thanks again kaz, I think I see what you mean know.

And it's pretty much what appears in Altera generated waveforms (which I joined). It takes one dummy read cycle, where outputs are 'X' and after that, one dummy write cycle (read of 000 and 001 addresses) and the outputs become valid.

However, after that dummy write cycle, is it OK to read anywhere in the RAM, or do you need to write everywhere (at every location) before reading everywhere?