Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorIP AltsyncRam -- Read/Write operations issue
Hi all, I have another issue using the RAM IP core generated with the MegaFunction wizard. Here's the entity of my RAM and its instanciation:
GENERIC(
ADDRESS_WIDTH : IN INTEGER ;
PIXE...
Altera_ForumHonored Contributor
Honored ContributorWhen you leave that box blank it means no initialisation.
You shouldn't worry about 'x' states if your application doesn't care. So you can keep your write/read cycles. It will be the first read that causes 'x' which may be too visible or not in simulation depending on pipeline. Once a location is written to then it is readable as many times as you wish. If you want cosmetic surgery then you can initialise all to zeros with a file.
