IP AltsyncRam -- Read/Write operations issue

Thanks kaz for the reply,

I thought the altsyncram contents were initialized at '0' when you tick the "No,leave it blank" box under MegaFunction wizard, in the "Mem Init" tab.

I mean, I 've already run that sequence of operations with an altsyncram (READ, then +1 on q_a, then WRITE) only it wasn't pipelined. It worked like a charm. Only, during the first run, I only got zero's on q_a bus.

Thinking of that, when I did that, my read_enable and write_enable signals were only asserted for the presentation of data and address. After I switch them back to '0'. Whereas here it's not the case, they are always asserted.

Could this be the issue?