Hello! I want to interpolate a 13.5 kHz sinus signal, which is generated with a NCO at a sampling rate of 54 Khz. I want a sampling of 5,4 MHz. So i tried to use a CIC-Filter with rate = 100. What I get at the output of the CIC-Filter is a 4.5 kHz sinus signal !! --> there is something wrong! What is the problem here ?? I tried different types of stages and delays, but I won't get a 13.5 sinus. please help me.. Thanks!

it could be useful a post of your schematic. How many samples has a single period of the high frequency sine signal at the output?

The samples at the output are ok. It has to be 400 samples right?? I proof that with an analog oscillator. Maybe you have a look at the image... Thanks for your help!

i think there is a problem with your CIC hardware, because input samples should be synchronized with c0 clock and output samples should be synchronized with c1 clock. Note this, for every input sample 100 samples must go out. In your hardware, an input sample (synchronized with c0) is read 100 times by a module clocked with c1. As you are using two clocks, in your CIC hardware a dual-clock FIFO for crossing clock domains must be included.

Ok. I was thinking in your way too. Because the differentiators has to be clocked with the lower sample rate and the integrators has to be clocked with the higher rate. But I thought the CIC-Filter would do this "clocking" automatically. The CIC-Filter generated by the MegaWizard has only one clock-input.....how should I solve the problem??...

so, you are driving in the wrong way the avalon-streaming signals. in_valid line must be asserted every 100 cycles of 54 MHz clock.

Interpolation with CIC Filter | Altera Community

15 Replies

Altera_Forum
Honored Contributor
16 years ago
Again I don't know about your set-up and IP signals. But the role is 1:100.
It is your responsibility to clk data in at 1/100 of output rate. Then it is the responsibility of CIC IP to give you the correct output.
One way is this enable at a rate of 1/100, connect to valid_in:

-- detect the edge of slow clk in the fast clk domain:

wait until fast_clk = '1';
clk_1d <= clk_in;
clk_2d <= clk_1d;

enable <= clk_1d and not clk_2d;

edit: make sure clks are synchronised
Altera_Forum
Honored Contributor
16 years ago
Hello kaz !!
Now the CIC-Filter is working!
With detecting the edge of the slow clock and insert this to the Valid_In.
Thank you very much!
Tobias
Altera_Forum
Honored Contributor
11 years ago
Hi tobias ,are you here ? I found your question about cic filter and is helpful to me, can you upload your worked design of cic filter quartus project here ? Thanks !
Altera_Forum
Honored Contributor
11 years ago
Ok. I was thinking in your way too. Because the differentiators has to be clocked with the lower sample rate and the integrators has to be clocked with the higher rate. But I thought the CIC-Filter would do this "clocking" automatically.
The CIC-Filter generated by the MegaWizard has only one clock-input.....how should I solve the problem??...

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Altera_Forum
Honored Contributor
11 years ago
The CIC core has a streaming interface involving input and output valid signals rather than separate "clocks". The output rate will be in fact generated automatically with respect to the input rate. Review the documentation!

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Interpolation with CIC Filter

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