Interpolation with CIC Filter

Again I don't know about your set-up and IP signals. But the role is 1:100.

It is your responsibility to clk data in at 1/100 of output rate. Then it is the responsibility of CIC IP to give you the correct output.

One way is this enable at a rate of 1/100, connect to valid_in:

-- detect the edge of slow clk in the fast clk domain:

wait until fast_clk = '1';

clk_1d <= clk_in;

clk_2d <= clk_1d;

enable <= clk_1d and not clk_2d;

edit: make sure clks are synchronised