Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Internal memory usage using MegaWizard RAM: 2-port

Hi, I am using 8k, 8-bit wide internal 2-port RAM. Here's the instantiation in Verilog: working_ram ram_test ( .data(ram_data_test), // input [7:0] data; .rdaddress(ram_rd_add...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

yeah, forgot to mention that although I've separate rd and wr clks, for testing I'm using same module_test_clk for rd and wr.