Interfacing custom logic to SDRAM controller IP without using NIOS

Hello,

Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller?

I have written the simplest code I could think of to test that I can use the SDRAM controller in my SOPC Builder system: writing 1 x 16-bit word of data to SDRAM using my own Avalon MM Master (in Verilog). The code is:

// Shift register for host_rst_l

always @(posedge host_clk or negedge host_rst_l)

begin

if (~host_rst_l)

host_rst_l_sr <= 2'b0;

else

host_rst_l_sr <= {host_rst_l, host_rst_l_sr[1]};

end

// State Machine which writes to and reads from SDRAM Controller

always @(posedge host_clk or negedge host_rst_l)

begin

if (~host_rst_l)

begin

state <= 4'h0;

sdram_read <= 1'b0;

sdram_write <= 1'b0;

sdram_writedata <= 16'h0;

debug_sdram_readdata <= 8'h0;

sdram_byteenable <= 2'b0;

end

else if (host_rst_l_sr == 2'b10)

state <= 4'h1;

// Write Operation

else if (state == 4'h1)

begin

state <= state + 1'b1;

sdram_write <= 1'b1;

sdram_writedata <= 16'h28;

sdram_addr <= 24'h0;

sdram_byteenable <= 2'b11;

end

else if ((state == 4'h2)&(~sdram_waitrequest))

begin

state <= state + 1'b1;

sdram_write <= 1'b0;

end

// Read Operation

else if (state == 4'h3)

begin

state <= state + 1'b1;

sdram_read <= 1'b1;

sdram_addr = 24'h0;

sdram_byteenable = 2'b11;

end

else if ((state == 4'h4)&(sdram_readdatavalid)&(~sdram_waitrequest))

begin

state <= 4'h0;

debug_sdram_readdata <= sdram_readdata[7:0];

sdram_read <= 1'b0;

end

end

I don't get any response from the SDRAM controller. Can anyone see what I'm doing wrong - my understanding is that the above code complies with the Avalon MM spec.

best regards,

John