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Honored Contributor
Honored ContributorInterfacing custom logic to SDRAM controller IP without using NIOS
Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Here is one training course you may find useful before digging into it: http://www.altera.com/education/training/courses/oqsys3000 --- Quote End --- Thank you very much. That is very useful!
