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Honored Contributor
Honored ContributorInterfacing custom logic to SDRAM controller IP without using NIOS
Hello, Does anyone have experience of writing their own Avalon MM master port in Verilog to interface to the Altera SDRAM controller? I have written the simplest code I could think of to t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You can use the DMA or SGDMA to control the ext. memory, you just build a simple FSM to read the status of the DMA or write the control data to the DMA's register and monitor the state of the DMA. You must first read the AVALON specification and get a little inspection into the AVALON-MM master, it is very simple. Badoman is right, take the advantage of SOPC or QSYS, it can save you lots of time in coding the glue logic between your logic and ext. memory controller, especially when you change your design. You can just click and click, then a design is finished. --- Quote End --- How can I merge my own code into qsys? It seems that no tutorial about this.
