Interfacing Avalon On-Chip Memory Core to a custom Avalon MM Master

Hello,

I am trying to implement a custom Avalon MM Master to write into an On-Chip memory. This memory will later be accessed by a PCIe megafunction. My input is a data stream from a camera. As such, I thought there is no use in implementing a waitrequest signal, as the camera will not wait with supplying new data. However, the Avalon MM Master interface requires a waitrequest signal to be implemented("... all Avalon-MM master ports compulsorily support variable wait-states."), and throws errors when I don't do so and try to connect it to the memory(Error: memory.onchip_memory2_0.s1: Master avalon_master_1_1_1_1 does not have a waitrequest signal. Slave must match master's read and write wait time (read:1 write:1) ). The s1 latency here was 1 cycle on the memory.

The thought process would be to have the memory used as a kind of FIFO-like circular frame buffer by circulating addresses, where the data is written in the memory by frames, the memory stores multiple frames, and the PCIe megafuction reads the frame put in 1-2 frames before the current frame(so the read and write never points to the same place). As such, the interrupt signal would be sent after every frame to the megafunction, and it would free up much of the CPU.

I thought of using the Avalon ST Streaming interface for this, but that can't access the memory addresses as I would like to.

Could anyone advise me what to do in this situation?