Interfacing Avalon On-Chip Memory Core to a custom Avalon MM Master

Thank you for your answer, I have since then come up with another solution.

The problem has been also modified a bit, but as of now I would approach the problem like this: In most cases if you are transferring some data to a memory, you are not happy if some data gets lost in the process.

Thus for these cases, ignoring the waitrequest signal, as you suggested is not a good idea(though it is a solution for the exact problem). The solution for this is to implement a FIFO between the memory and the signal source in such a way, that the read from the FIFO is stalled when the waitrequest is asserted from the memory. If there are large enough pauses between the data writes to the FIFO( in the camera example, blanking) then a single clock FIFO can be used; otherwise a dual clock FIFO with a faster clock on the memory side should be used.

This can be implemented using the Avalon MM interface, but as the Avalon MM FIFO is slave from both sides, you have to implement the writing and reading logic to and from the FIFO yourself.

I hope this will be helpful for someone :)