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Raj_G's avatar
Raj_G
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3 years ago
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intel_rtile_cxl_top_0_ed PIPE Simulation support?

Is it possible to run the intel_rtile_cxl_top_0_ed (Agilex R-Tile Intel FPGA IP for Compute Express Link (CXL)) simulation via the PIPE interface? Or is only the serial interface supported for simulation?

  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi

    We have not hear from you and this Case is idling. It is not recommended to idle for too long.

    Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel


6 Replies

    • Raj_G's avatar
      Raj_G
      Icon for New Contributor rankNew Contributor
      3 years ago

      Wincent_Intel,

      Thanks for the link, but this doesn't cover the CXL IP, it just says it works for the PCIe IP. Is the support and how to configure it for PIPE mode similar to the PCIe IP?

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,


    You may click the latest version of the document.

    For more details on the Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP and the corresponding design examples, refer to:

    • Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP User Guide. This document is available in the Intel Resource and Documentation Center (RDC). You can download a copy or ask your local Intel Field Applications engineer to download one using the asset number 763328.
    • Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP Design Example User Guide. This document is available in the Intel Resource and Documentation Center (RDC). The asset number is 763513.


    Those are the available resource for CXL R-tile. Hope this clarified.

    Regards,

    Wincent_Intel


    • Raj_G's avatar
      Raj_G
      Icon for New Contributor rankNew Contributor
      3 years ago

      Sorry for the delay, this helped. Once I was able to get the documents.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi

    We have not hear from you and this Case is idling. It is not recommended to idle for too long.

    Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel