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Raj_G's avatar
Raj_G
Icon for New Contributor rankNew Contributor
3 years ago
Solved

intel_rtile_cxl_top_0_ed PIPE Simulation support?

Is it possible to run the intel_rtile_cxl_top_0_ed (Agilex R-Tile Intel FPGA IP for Compute Express Link (CXL)) simulation via the PIPE interface? Or is only the serial interface supported for simul...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi

    We have not hear from you and this Case is idling. It is not recommended to idle for too long.

    Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel