Forum Discussion
New Contributorintel_rtile_cxl_top_0_ed PIPE Simulation support?
Hi
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
If you feel your support experience was less than a 9 or 10,
please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.
Regards,
Wincent_Intel
Regular ContributorHi,
You may click the latest version of the document.
For more details on the Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP and the corresponding design examples, refer to:
- Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP User Guide. This document is available in the Intel Resource and Documentation Center (RDC). You can download a copy or ask your local Intel Field Applications engineer to download one using the asset number 763328.
- Intel® Agilex™ R-Tile Compute Express Link 1.1 Intel FPGA IP Design Example User Guide. This document is available in the Intel Resource and Documentation Center (RDC). The asset number is 763513.
Those are the available resource for CXL R-tile. Hope this clarified.
Regards,
Wincent_Intel
Raj_GSorry for the delay, this helped. Once I was able to get the documents.
