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10's avatar
10
Icon for New Contributor rankNew Contributor
5 years ago

Intel P tile PCIE avmm for Stratix 10DX device

Hi , I integrated P tile PCIE avmm with 4 DDR memory. I am having doubt on connections in platform designer. PCIe parameters: gen3x16 is used with end point mode. i am not getting proper...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi 10,

With the screenshot, it is hard to look on it and understand in full picture. Perhaps you should attach the platform designer file (.qsys).

By the way, you can look on the existing reference design (PCIe-DDR4) and compare it with your design?

https://fpgacloud.intel.com/devstore/platform/18.1.0/Pro/pci-express-gen3-x16-avmm-dma-with-ddr4-memory-reference-design/

Lastly, I can see you connect the emif_usr_clk to an IOPLL ref clock, this is looks like PLL cascading, I am wonder fitter allow you to pass the compilation?


  • 10's avatar
    10
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi

    thanks for the reply.

    i will share my qsys file and please check it out if any changes mention it

    Thanks in advance