Altera_Forum
Honored Contributor
14 years agointegrate SDRAM and Flash in Qsys
hello everyone,'m quite newbie in Quartus 10.1.Rightnow i m working on a project in which i need to work on quartus 10.1 (sp1),so as u all might know that there is one new feature of Qsys in Quartus 10.1.And in qsys,there is no directly provision of tristate bridge to which sdram and flash -data and address lines are shared.
Instead there are 3 stages for creating tristate bridge (generic trisate controller,pin sharer,tristate bridge) I have read "qsys interconnect" and design examples also provided by that.in which they have given some notes on this,but i don't know how to interface them,i have tried but not able to understanding means how to set the parameters for both of them in generic tristate con.??:( So anyone please post sample and very small Qsys system or just a screen shot containing "clock source,nios II,jtag uart,timer,sdram,flash,pll"???? Any idea or suggestion would b greatly appreciated.:)