New Contributor
Regular ContributorHi,
As I understand it, you are observing some mismatching between the FFT HDL simulation vs the hardware testing. Would you mind to further elaborate on your issue obseration ie no SOP/EOP observed in hardware? Some signaltap will be helpful for better understanding. Thank you.
New ContributorThank you chee pin.i am attaching the screenshot for your reference.
Addition of info:
We are getting below messages as critical warning which is under FFT IP core:
Memory depth (514) in the design file differs from memory depth (513) in the Memory Initialization File "IPs/new/FFT_NEW/altera_fft_ii_191/synth/FFT_NEW_altera_fft_ii_191_3lkhdja_opt_twr1.hex" -- setting initial value for remaining addresses to 0
Memory depth (130) in the design file differs from memory depth (129) in the Memory Initialization File "IPs/new/FFT_NEW/altera_fft_ii_191/synth/FFT_NEW_altera_fft_ii_191_3lkhdja_opt_twr2.hex" -- setting initial value for remaining addresses to 0
Memory depth (34) in the design file differs from memory depth (33) in the Memory Initialization File "IPs/new/FFT_NEW/altera_fft_ii_191/synth/FFT_NEW_altera_fft_ii_191_3lkhdja_opt_twr3.hex" -- setting initial value for remaining addresses to 0
Memory depth (10) in the design file differs from memory depth (9) in the Memory Initialization File "IPs/new/FFT_NEW/altera_fft_ii_191/synth/FFT_NEW_altera_fft_ii_191_3lkhdja_opt_twr4.hex" -- setting initial value for remaining addresses to 0
Memory depth (4) in the design file differs from memory depth (3) in the Memory Initialization File "IPs/new/FFT_NEW/altera_fft_ii_191/synth/FFT_NEW_altera_fft_ii_191_3lkhdja_opt_twr5.hex" -- setting initial value for remaining addresses to 0
Not sure why we are getting these warnings. Any chance it effects FFT IP Core working on board. We are seeing output correctly in simulations.
Whereas on board source control and data signals are behaving differently.
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