Forum Discussion

alinave's avatar
alinave
Icon for New Contributor rankNew Contributor
6 years ago

In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

The Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core user guide suggest that the input reference clock pin to the ATX PLL must be a dedicated reference clock pin (2.4.2. Adding the Transceive...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Naved,

After further consultation with internal team, actually both design connection also fine

  • option 1 : use 2nd ATX PLL as PLL
  • option 2 : use 2nd ATX PLL as clock buffer

It's just that the option 2 "use 2nd ATX PLL as clock buffer" seems to perform better as compared to option 1.

Therefore, Intel engineering team plans to amend existing example design to use option 2 in future Quartus release.

We won't be changing the user guide doc explanation anymore as it's a preferred recommendation.

Thanks.

Regards,

dlim