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Altera_Forum
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13 years ago

In qsys,can PCIe IP receive write request that exceeds 512 bytes?

We design our fpga project based on cyclone iv EP4CGX15 without external ram. Since PCIe IP spec says: "A Qsys-generated PCI Express Avalon-MM bridge accepts Avalon-MM burst write requests wit...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The SGDMA/DMA will generate a lot of smaller Avalon bursts, each is (probably) processed separately.

The maximum sized PCIe packet is (probably) 128 bytes, so there is probably little reason for the DMA to generate longer bursts.

PCIe supports multiple outstanding requests - and I presume the Altera PCIe master is capable of generating them - so you only get very marginal throughput improvements for very long TLP (short ones are very slow - especially if synchronous).