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Altera_Forum's avatar
Altera_Forum
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17 years ago

Implementing HT protocol

Hi Guys, am new here!

I need to implement a HT link between stratixII and AMD opteron. I have to transport the data from LVDS link in FPGA to AMD via HT. Can anyone tell me what is easiest way of implementing this? I am using @ltera HT cores, composed of 3 buffers posted, non-posted and response. Basic question, Do I need to use all of these buffers? or posted is enough for writing purpose...I am not reading anything from AMD its just 1way communication. It just dumping the data to AMD at high speed.

Can anyone suggest me best book for HT?

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Excuse the plug, but you might want to look at www.xtremedata.com. It's a pretty cool system where they take FPGAs and put them on a custom board that plugs directly into the Opteron Socket F. The FPGA interfaces(Hypertransport to the other Opteron/s, memory, etc.) are already taken care of for you. Naturally, if you need something else customized for your system, it may not work, but it's a pretty neat way to quickly get FPGA accelerators onto COTS systems.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thanks for your reply!

    We are looking for customized solution to implement on our board. I am not aware of how to use HT userend interface, when I need to write data to the CPU. Is it okay to use only TX interface? (TX_Posted for write) or need to respond RX_Response from CPU?

    As I see 3 buffers on TX side used for different puspose, like write/read and respond....