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Altera_Forum
Honored Contributor
Honored ContributorImplementing Cache Memory for Custom Logic
How can I implement a cache memory for look-up purposes which works with my custom logic, not Nios or ARM? I have implemented different cache architectures using VHDL or Verilog, pipelined them, w...
Altera_ForumHonored Contributor
Honored ContributorI'm not aware of any bundled IP that would implement a cache as you would like.
What you would need to do is either create your own, or pull together enough pieces from the internet to create your own. Skimming opencores.org, nothing jumps out as immediately usable. There is an empty project for something which would have most likely been an exact fit for you: http://opencores.org/project,level2_cache_nios_iie Good luck!
