Hi Pete,
Thank you for your answer. In fact I have another way to deal with it.
The main clock is about 200 MHz, the data rates can be between 150 kHz and 2 MHz appproximately. The size of the FFT can be between 64 and 512 points. But I use a large FPGA, so I can put a lot of FFTs inside.
But now my idea is to multiplex the data stream, write them into a buffer, then read them (the addresses are not accessed in the same order for the writing and the reading, which implies in fact to have two buffers working in ping-pong) and process them with only one FFT ! Like this it is much simpler and much more efficient.
Jérôme