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Altera_Forum
Honored Contributor
Honored ContributorIIR in DSP-Builder with modified multiplier LUT or multiplie accumulate
Hi, I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someon...
Altera_ForumHonored Contributor
Honored ContributorI make a Simulation in matlab with the same clock of 48kHz, the simulation was correct. But with the signal compiler dsp-builder I became a error
--> out of memory quartus-map.exe 1881 MByte wath is the problem?
