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Altera_Forum
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16 years ago

IIR in DSP-Builder with modified multiplier LUT or multiplie accumulate

Hi, I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someon...
Altera_Forum's avatar
Altera_Forum
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16 years ago

can you provide some extra information? do the filters have the same coefficients? what is the sample rate and available clock rate? how many bits are the data and coefficients?

you should be able to take HDL for an IIR and use LE based multipliers instead of DSP blocks by using synthesis attributes or instantiating MegaFunction multipliers.