DDaoNew Contributor7 years agoI used Intel SERDES IP for my design on the Arial 10 SoC devlp kit, configured to loop back mode (64 bits output => SERDES => Serial data => SERDES => 64 bits input). It showed a lot of bit flips in the 64 bits input. Do you have any ideas? Thanks
1 ReplyReplies sorted by Most LikedRahul_S_Intel1Frequent Contributor7 years agoHi , Kindly use the example design first that is generated from the IP, so that any setting error can be isolated. Regards, Rs
Rahul_S_Intel1Frequent Contributor7 years agoHi , Kindly use the example design first that is generated from the IP, so that any setting error can be isolated. Regards, Rs
Recent DiscussionsCyclone IV GX project failed migration from 20.1 to 23.1stdCyclone 10 GX IBIS-AMI modelsPCIe Enumeration Failure for CXL IPCan't generate F-Tile Ethernet Hard IP Design ExampleAgilex 7 slew rate reconfiguration