I need a help with simulation RTL DDR2 SDRAM Controllers with ALTMEMPHY for CycloneIV

Hi.

I'm trying to simulate the DDR2 in QUARTUS 10.1sp1 + Active-HDL 8.3sp1 with NativeLink. I simulate the test example. Settings:

Controller data rate - full. Enable Half Rate вridge - off.

Controller Architecture - High Perforrnance Controller ll.

Sarnsung K4T1G164QF. The remaining default settings.

Message is displayed in Active-HDL:

# File: D:\DinamWork\Cmosis1\simulation\activehdl\cmosis1\src\cmosis_example_top_tb.vhd

# Compile Architecture "rtl" of Entity "cmosis_example_top_tb"

# Compile success 0 Errors 0 Warnings Analysis time : 14.0 [s]

# ELBREAD: Elaboration process.

# ELBREAD: Elaboration time 0.4 [s].

asim +access +r -t 1ps -L cmosis1 -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive -L cycloneiii testbench/cmosis_example_top_tb.vhd

# Error: Cannot find library 'testbench/cmosis_example_top_tb' in the Design Browser

# Error: DO_001 in file cmosis1_sim_rtl_vhdl.do line 61.

Can not understand where the error is.

When I'm trying to simulate the DDR2 in QUARTUS 10.1sp1 + Active-HDL 8.3sp1 without NativeLink.

Message is displayed in Active-HDL:

# Warning: VCP2515 cmosis_phy_alt_mem_phy.v : (628, 1): Undefined module: cmosis_phy_alt_mem_phy_write_dp was used. Port connection rules will not be checked at such instantiations.

Where can I get this cmosis_phy_alt_mem_phy_write_dp?