Forum Discussion
KennyT_altera
Super Contributor
5 years agoWhat u can do is use the tecnology map viewer to look into the netlist.
-asynch Traverse through asynch edges, this normal happened on after LUT1 where no clock involve.
-synch Traverse through synch edges, usually, on the register where clock is involve.
-clock Traverse through clock edges, on the clock path rather than the data path. for example, output of PLL.