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Altera_Forum
Honored Contributor
Honored ContributorHPC Memory Controller Write but can't Read
Maybe somebody can help here with this. I have hooked up a HPC memory controller to my SOPC system, configured it the way it is going to be used and everything. No problem with generating, it synth...
Altera_ForumHonored Contributor
Honored ContributorHPC...
We discovered a bug in the HPCII and Altera is working on it. We are also using the altmemphy. I mis-read signal tap. The data never appears on the readdata bus. Immediately at assertion of the read, the cpu_data_master_waitrequest is asserted and never deasserted. The local_read_req is asserted for 2 sample cycles (nios system clock) and then deasserts, leaving local ready and cpu_data_master_waitrequest asserted. ?????
